The issue I described as “blue tint” turns out to have been a fault in my test system. I built another revision of the PCB including pads for capacitors, and it would seem I only needed to place a cap on the clock line to resolve the remaining signal integrity issues.

Current Status

• Full VGA Clock (25.175MHz) without any pixel errors / artifacts
• Full brightness control via the contrast keys
• Less than 100µA draw on the 10.5V inverter supply while display is off.
• All electrical load is on the inverter supply wires and not the fpc.
• 250mA fuse to reduce risk of blowing the internal 650mA fuse in any unexpected failure modes.
• Using the Hitachi transceivers maintains same electrical interface to the CT65535 as the OEM display. This may be an overkill step but it is working well so I am sticking with it.

Next Steps

• Further verify there are no pixel errors at the higher clock speed.
• Revise the PCB to simplify assembly and clean it up.
• Update the 3d model for the new bezel to accommodate the new PCB.

Current Revision

This is just a quick update. This is more a journal to myself and as always I most say I do not know what I doing generally, so consider this as entertainment more than information.

TLDR: I have had some success using the Hitachi level converters and terminating capacitors. I believe this issue is all about transmission line theory, which I am aware of but do not understand so this is trial and error. I am ordering another revision of the board this week and starting to try and finalize the 3D model for the bezel.

I do still notice a blue tint in certain mode tests, I am not certain this is a hardware issue yet I need to investigate it more once these other issues are sorted out.

I continue to chase the goal of being able to drive the replacement display at the full VGA clock speed of 25.175MHz / ~60hz refresh rate.

To summarize the issues I have been facing, in various versions of the PCB’s and hand wiring there was noise, jitter and other timing issues visible when certain patterns were displayed on the screen. The effect was not as bad when running at 15MHz but still there. It was terrible with sloppy handmade boards and breadboard testing.

I attempted to fix this with various forms of shielding, however it became clear the the issue was not external noise, and the reason the the metal back plate improved the situation was due to some kind of inductive coupling or similar effect on the ribbon cable.

I concluded the issue was related to an impedance mismatch causing reflections of the signal. I looked at what type of source termination and receiver end termination may have been in place.

I found that all signals including the clock appear to have a 0ohm resistor between the CT65535 output pin and the FPC connector, and they are each coupled to ground with a 50pf or so capacitor. On receiving side they went straight into a Hitatchi HD151015 9 bit Level Shifter / Transceiver.

I figured these values and topology were designed based on the length of the path from the CT65535 through to the CSTN at the original clock speed (~8mhz if i recall).

Of course this is no longer the case with the adapter board where two new connectors are introduced, the traces on the adapter PCB, the ribbon cable on the AT050TN23v1 and then the difference of the input gates/etc on the TFT.

I had various attempts at implementing signal termination at the converter PCB and on the TFT DCLK pin itself with varying success but nothing repeatable. What would work with test leads would not work once soldered on. What worked in one orientation would not work in another it was all random. I believe this may have at least in part been related to trying to terminate in the middle of the transmission line and not close enough to the end.

It had also been observed that lowering the voltage of VCC on the TFT could improve the issue slightly, this was not practical but got me thinking about level converters to address the flight difference the PC110 ~3.5V and the 3.3V of the DC-DC. I also knew that the immediate input on the OEM display was a Hitatchi level converter.

I purchased every possible level converter I could find on digikey, and generally the results were identical to it not being used at all. I then tried harvesting the Hitatchi level converters off an old CSTN and suddenly the signal was drastically improved, but still had some issues which I assumed was related to the hand wiring used for testing

I produced a PCB to properly mount the Hitachi chips and upon initial testing there was almost identical issues with the signal/display as without the Hitachi chips. This was starting to solidify a sense of defeat.

Due to missing (still missing) digikey delivery I was without the various capacitors to mount on the board, so there was still a small hope that the bypass capacitors on the level converters could help but not likely.

I then thought again if the previously attempted termination methods that failed would now have better luck given the long transmission line from the PC110 was now being terminated into the Hitatchi chip. Magically now, coupling the clock signal to ground with a 100nF capacitor at the input to the Hitatchi made the signal essentially perfect. Although I have not found issues yet, I expect there may be test images that result in some individual signal lines approaching clock speed and can benefit from the same filtering. Now I understand the issue is more about the speed of the transmission and not the frequency itself, but in practice it seems to be related to the frequency in this case.

I am going to order another revision of the PCB that will place 100nF capacitors as close to the Hitachi pins as possible. It is possible this approach may work with other actively available level converters but given the low volume of this project harvesting hitatchi chips from old displays and/or purchasing some limited qty of new old stock is good enough. It is also nice that the Hitachi chip has 9 channels allowing to accomplish the task with two chips, whereas most of the new parts are only 8 channel. The board is tight and my routing skills are limited.

Again in closing, I believe this all falls within “transmission line theory”, and with proper understanding it may be possible to simply place series resistors and/or capacitors on the converter board and with a correct value and solve the problem with less components i.e. no converters.

I am however taking the route of using the level converter chips to deal with the fact there is a difference between the Vcc from the 3.3V DC-DC and the “3.3V” on the PC110 motherboard. Putting the capacitors on the signal lines should create an RC filter, but I am not putting a resistor as I am assuming (from experimental testing) that the resistance of the trace/gate/etc is acceptable.

I am still trying to figure out what to do with the all of the signals but the clock signal in particular is of concern. It seems that the integrity of this signal may be the main cause of the distortion seen when running at 25.175MHz and even some at 15MHz. The distortion can be as simple as a single pixel shadow to the right on a black screen, or in more severe cases it appears as “jitter”. Previously we have attempted to compensate for this by lowering Vcc on the TFT display to try and have it handle the poor signal levels due to the assumed reflections. This signal integrity issue exists on all the signals, but the clock is the worst which is why I spent some time focusing on it. Maybe correction of it alone is not enough. Do I need to put level shifters/buffers onto the PCB?

I do not know what I am doing here, so if anybody knows better please help!

My measurement technique is almost certainly not correct and will be a contributing factor to the deformation/distortion of these measurements.

As we are looking for a solution that does not involve any modifications to the PC110 itself, there are only

• Clock Speed
• PCB Routing
• Bus Transceiver
• End Termination
• CT65535 Drive strength paramter (XR6C bit2)

Clock Speed

One complete frame is 525 lines. Each line is around 800 clock ticks. That means about 420k clock ticks per frame. So at 25.175MHz the refresh rate is around 60hz. At 15MHz it is closer to 35Hz. My goal is 25.175MHz still.

PCB Routing

I already have the trace quite short, however I think I can do better to reduce the sharp edges and surround it better with grounds. I will do more reaching on this and try to look at other designs for examples.

Bus Transceiver

Maybe this is too complicated and not needed, but maybe it is needed to use a voltage level translator much like what is found on the citizen board. I could place three of these 8 channel chips to handle all signal lines, so no longer a need to worry about the voltage difference between the PC110 “3.3V” and the TFT’s Vcc, as well the signal is regenerated.

https://www.digikey.ca/en/products/detail/texas-instruments/SN74AVC8T245DGVR/774199

End Termination / Drive Strength

Termination is a complex topic for me. I have no chance to calculate what is needed so it will be trial and error. I am contemplating how to place the appropriate pads to allow experimentation the potential termination methods (single parallel resistor, RC, Thevenin, Schottky diode) etc, but without further aggravating the issue of reflect with all those little unused pads.

I already experienced this issue, where I found a nice combination of capacitors (through trial and error) that made the signal perfect, however I was testing with long wires, when I then put the components onto the TFT it did not work because the situation was totally different without those long wires.

Depending on the termination choice taken, maybe it will be needed to increase the drive output of the CT65535 via XR6C bit 2.

Citizen Display Attached

Although waveform doesnot look ideal, you can see at least that the reflection is not so serious and it is close to 3V Vpp with minimum at 0.

The following is the clock waveform measured as it exits the hitachi level shifter on the CSTN control board.

No Connection

This is what it looks like with no display attached

AT050TN23v1

This is waveform with TFT attached.

PC110 DRIVING SIDE

The digital clock output from the CT65535 (Pin B8) connects to the LCD output connector Pin29 via a 0ohm jumper, and is coupled to ground with a 50pf capacitor. I would suspect the 0ohm jumper was a provision for driver side termination? there is no trace running under it so it was not for routing purposes.

On the Citizen display all signals are fed into level shifters.

The following is an updated version of the experimental vpatch. It reads from a config.txt for the values to update in memory, this is to make it easier to verify which values need to be updated without rebuilding the program every time.

the first line is a checksum, if you set it to 0 the program will not check and will update and reboot every time. If you set an expected checksum, it will only update/reboot if that matched, which is good for putting in autoexec.bat

the program has very limited error checking and very simple parsing of the config file so you have to be specific.

this program is the precursor to flashing the chip.

This is the preliminary design for the V3 PCB. I will update this post with better details tomorrow. I noticed some not so nice routing I need to fix/clean up.

Summary:

• Support for AT050TN23v1 display module only
• Take power from the inverter connector
• Uses PIC microcontroller to generate the PWM signal for the LED backlight intensity based on the level of the constrast/lcd driver output (Fn-Ins/Del)
• Resistor values will be confirmed later. if needed the MCU program can “learn” the minimum and maximum voltages to give the best resolution possible.
• Uses the premade DC-DC converters that are mounted on the back, I don’t think noise will be an issue.