I am still trying to figure out what to do with the all of the signals but the clock signal in particular is of concern. It seems that the integrity of this signal may be the main cause of the distortion seen when running at 25.175MHz and even some at 15MHz. The distortion can be as simple as a single pixel shadow to the right on a black screen, or in more severe cases it appears as “jitter”. Previously we have attempted to compensate for this by lowering Vcc on the TFT display to try and have it handle the poor signal levels due to the assumed reflections. This signal integrity issue exists on all the signals, but the clock is the worst which is why I spent some time focusing on it. Maybe correction of it alone is not enough. Do I need to put level shifters/buffers onto the PCB?
I do not know what I am doing here, so if anybody knows better please help!
My measurement technique is almost certainly not correct and will be a contributing factor to the deformation/distortion of these measurements.
As we are looking for a solution that does not involve any modifications to the PC110 itself, there are only
- Clock Speed
- PCB Routing
- Bus Transceiver
- End Termination
- CT65535 Drive strength paramter (XR6C bit2)
One complete frame is 525 lines. Each line is around 800 clock ticks. That means about 420k clock ticks per frame. So at 25.175MHz the refresh rate is around 60hz. At 15MHz it is closer to 35Hz. My goal is 25.175MHz still.
I already have the trace quite short, however I think I can do better to reduce the sharp edges and surround it better with grounds. I will do more reaching on this and try to look at other designs for examples.
Maybe this is too complicated and not needed, but maybe it is needed to use a voltage level translator much like what is found on the citizen board. I could place three of these 8 channel chips to handle all signal lines, so no longer a need to worry about the voltage difference between the PC110 “3.3V” and the TFT’s Vcc, as well the signal is regenerated.
End Termination / Drive Strength
Termination is a complex topic for me. I have no chance to calculate what is needed so it will be trial and error. I am contemplating how to place the appropriate pads to allow experimentation the potential termination methods (single parallel resistor, RC, Thevenin, Schottky diode) etc, but without further aggravating the issue of reflect with all those little unused pads.
I already experienced this issue, where I found a nice combination of capacitors (through trial and error) that made the signal perfect, however I was testing with long wires, when I then put the components onto the TFT it did not work because the situation was totally different without those long wires.
Depending on the termination choice taken, maybe it will be needed to increase the drive output of the CT65535 via XR6C bit 2.
Citizen Display Attached
Although waveform doesnot look ideal, you can see at least that the reflection is not so serious and it is close to 3V Vpp with minimum at 0.
The following is the clock waveform measured as it exits the hitachi level shifter on the CSTN control board.
This is what it looks like with no display attached
This is waveform with TFT attached.
PC110 DRIVING SIDE
The digital clock output from the CT65535 (Pin B8) connects to the LCD output connector Pin29 via a 0ohm jumper, and is coupled to ground with a 50pf capacitor. I would suspect the 0ohm jumper was a provision for driver side termination? there is no trace running under it so it was not for routing purposes.
On the Citizen display all signals are fed into level shifters.